[Intel-wired-lan] [PATCH 2/5] e1000e: Increase PHY PLL clock gate timing

[Brown, Aaron F]

> From: Intel-wired-lan [intel-wired-lan-bounces at lists.osuosl.org] on behalf of Raanan Avargil [raanan.avargil at intel.com]
> Sent: Tuesday, December 22, 2015 5:35 AM
> To: intel-wired-lan at lists.osuosl.org
> Subject: [Intel-wired-lan] [PATCH 2/5] e1000e: Increase PHY PLL clock gate      timing
> 
> Several packet loss issues were reported for which the root cause for
> them was an incorrect configuration of internal HW Phy clock gating
> mechanism by SW.
> This patch provides the correct mechanism.
> 
> Signed-off-by: Raanan Avargil <raanan.avargil at intel.com>
> ---
>  drivers/net/ethernet/intel/e1000e/ich8lan.c | 12 ++++++++++++
>  drivers/net/ethernet/intel/e1000e/ich8lan.h |  3 +++
>  2 files changed, 15 insertions(+)

Tested-by: Aaron Brown <aaron.f.brown at intel.com>