[Intel-wired-lan] 答复: [PATCH] add one parameter wro_enable to enable relaxed ordering for IXGBE

maowenan maowenan at huawei.com
Wed Nov 9 09:43:36 UTC 2016


I have verified that the performance will be enhanced certainly when I enabled Relax Ordering on SPARC, but think it is not very flexible to disable or enable Relax Ordering feature using CONFIG_SPARC currently,
So I want to use module parameter to set RO instead of "#ifndef CONFIG_SPARC", no need to rebuild the whole kernel.


-----邮件原件-----
发件人: Jeff Kirsher [mailto:jeffrey.t.kirsher at intel.com] 
发送时间: 2016年10月29日 15:42
收件人: maowenan; intel-wired-lan at lists.osuosl.org; netdev at vger.kernel.org; linux-kernel at vger.kernel.org
主题: Re: [PATCH] add one parameter wro_enable to enable relaxed ordering for IXGBE

On Sat, 2016-10-29 at 15:08 +0800, Mao Wenan wrote:
> This patch provides a way to enable relaxed ordering, where it helps 
> with performance in some architecture.
> The default value of wro_enable is 0, if you want to enable relaxed 
> ordering, please set wro_enable=1.
> 
> Mao Wenan (1):
>   add one parameter wro_enable for IXGBE
> 
>  drivers/net/ethernet/intel/ixgbe/ixgbe.h        |  1 +
>  drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c  | 29 
> ++++++++++++++-----
> ------
>  drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 28 
> +++++++++++++----
> -------
>  drivers/net/ethernet/intel/ixgbe/ixgbe_main.c   |  9 ++++++++
>  4 files changed, 41 insertions(+), 26 deletions(-)

Why have a title patch for only one patch?  Better yet, the one patch does not have a patch description.  Get rid of the title patch and add the above information into the patches description.

In addition, module parameters are not kindly looked upon, one reason is that it cannot be standardized and enforced.

I am also confused because you are stating that on some architectures, yet this code is only compiled in when SPARC is defined and that there are times when you want relaxed ordering enabled and other times disabled?
 Your gonna have to provide more data on why, because the code as is was resolving serious performance issues on SPARC when relaxed ordering was enabled.


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