[Intel-wired-lan] [next PATCH S53 2/5] i40e: Add support for 25G devices

Shannon Nelson sln at onemain.com
Sat Nov 12 20:04:59 UTC 2016


On 11/11/2016 12:16 PM, Bimmy Pujari wrote:
> From: Carolyn Wyborny <carolyn.wyborny at intel.com>
>
> Add support for 25G devices.

Since adding support in this case includes changing the use of a couple 
of the FW interface fields and the types used in the PHY struct, I think 
a little more explanation would be helpful here to point out the trick 
being used to accommodate the additional PHY types.  That way, some 
random outsider won't get his panties all in a knot about losing the 
compiler type checking on the enum values. :-)

sln

>
> Signed-off-by: Carolyn Wyborny <carolyn.wyborny at intel.com>
> Signed-off-by: Michal Kosiarz <michal.kosiarz at intel.com>
> Signed-off-by: Eric Joyner <eric.joyner at intel.com>
> Signed-off-by: Mitch Williams <mitch.a.williams at intel.com>
> Signed-off-by: Henry Tieman <henry.w.tieman at intel.com>
> Signed-off-by: Avinash Dayanand <avinash.dayanand at intel.com>
> Change-ID: I69b24d837d44cf9220bf5cb8dd46c5be89ce490b
> ---
> Testing Hints : Check that 25G devices link and report
> correct device speed.
>
>   drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h  | 30 +++++++-
>   drivers/net/ethernet/intel/i40e/i40e_common.c      | 11 ++-
>   drivers/net/ethernet/intel/i40e/i40e_devids.h      |  2 +
>   drivers/net/ethernet/intel/i40e/i40e_ethtool.c     | 20 +++++-
>   drivers/net/ethernet/intel/i40e/i40e_main.c        |  6 +-
>   drivers/net/ethernet/intel/i40e/i40e_type.h        | 82 +++++++++++++---------
>   drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c |  3 +
>   .../net/ethernet/intel/i40evf/i40e_adminq_cmd.h    | 30 +++++++-
>   drivers/net/ethernet/intel/i40evf/i40e_common.c    |  2 +
>   drivers/net/ethernet/intel/i40evf/i40e_devids.h    |  2 +
>   drivers/net/ethernet/intel/i40evf/i40e_type.h      | 82 +++++++++++++---------
>   drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c |  8 +++
>   .../net/ethernet/intel/i40evf/i40evf_virtchnl.c    |  3 +
>   13 files changed, 202 insertions(+), 79 deletions(-)
>
> diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
> index 67e396b..c9d1f91 100644
> --- a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
> +++ b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
> @@ -1642,6 +1642,10 @@ enum i40e_aq_phy_type {
>   	I40E_PHY_TYPE_1000BASE_LX		= 0x1C,
>   	I40E_PHY_TYPE_1000BASE_T_OPTICAL	= 0x1D,
>   	I40E_PHY_TYPE_20GBASE_KR2		= 0x1E,
> +	I40E_PHY_TYPE_25GBASE_KR		= 0x1F,
> +	I40E_PHY_TYPE_25GBASE_CR		= 0x20,
> +	I40E_PHY_TYPE_25GBASE_SR		= 0x21,
> +	I40E_PHY_TYPE_25GBASE_LR		= 0x22,
>   	I40E_PHY_TYPE_MAX
>   };
>   
> @@ -1650,6 +1654,7 @@ enum i40e_aq_phy_type {
>   #define I40E_LINK_SPEED_10GB_SHIFT	0x3
>   #define I40E_LINK_SPEED_40GB_SHIFT	0x4
>   #define I40E_LINK_SPEED_20GB_SHIFT	0x5
> +#define I40E_LINK_SPEED_25GB_SHIFT	0x6
>   
>   enum i40e_aq_link_speed {
>   	I40E_LINK_SPEED_UNKNOWN	= 0,
> @@ -1657,7 +1662,8 @@ enum i40e_aq_link_speed {
>   	I40E_LINK_SPEED_1GB	= BIT(I40E_LINK_SPEED_1000MB_SHIFT),
>   	I40E_LINK_SPEED_10GB	= BIT(I40E_LINK_SPEED_10GB_SHIFT),
>   	I40E_LINK_SPEED_40GB	= BIT(I40E_LINK_SPEED_40GB_SHIFT),
> -	I40E_LINK_SPEED_20GB	= BIT(I40E_LINK_SPEED_20GB_SHIFT)
> +	I40E_LINK_SPEED_20GB	= BIT(I40E_LINK_SPEED_20GB_SHIFT),
> +	I40E_LINK_SPEED_25GB	= BIT(I40E_LINK_SPEED_25GB_SHIFT),
>   };
>   
>   struct i40e_aqc_module_desc {
> @@ -1690,7 +1696,13 @@ struct i40e_aq_get_phy_abilities_resp {
>   	__le32	eeer_val;
>   	u8	d3_lpan;
>   #define I40E_AQ_SET_PHY_D3_LPAN_ENA	0x01
> -	u8	reserved[3];
> +	u8	phy_type_ext;
> +#define I40E_AQ_PHY_TYPE_EXT_25G_KR	0X01
> +#define I40E_AQ_PHY_TYPE_EXT_25G_CR	0X02
> +#define I40E_AQ_PHY_TYPE_EXT_25G_SR	0x04
> +#define I40E_AQ_PHY_TYPE_EXT_25G_LR	0x08
> +	u8	mod_type_ext;
> +	u8	ext_comp_code;
>   	u8	phy_id[4];
>   	u8	module_type[3];
>   	u8	qualified_module_count;
> @@ -1712,7 +1724,12 @@ struct i40e_aq_set_phy_config { /* same bits as above in all */
>   	__le16	eee_capability;
>   	__le32	eeer;
>   	u8	low_power_ctrl;
> -	u8	reserved[3];
> +	u8	phy_type_ext;
> +#define I40E_AQ_PHY_TYPE_EXT_25G_KR	0X01
> +#define I40E_AQ_PHY_TYPE_EXT_25G_CR	0X02
> +#define I40E_AQ_PHY_TYPE_EXT_25G_SR	0x04
> +#define I40E_AQ_PHY_TYPE_EXT_25G_LR	0x08
> +	u8	reserved[2];
>   };
>   
>   I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
> @@ -1792,6 +1809,13 @@ struct i40e_aqc_get_link_status {
>   #define I40E_AQ_LINK_TX_DRAINED		0x01
>   #define I40E_AQ_LINK_TX_FLUSHED		0x03
>   #define I40E_AQ_LINK_FORCED_40G		0x10
> +/* 25G Error Codes */
> +#define I40E_AQ_25G_NO_ERR		0X00
> +#define I40E_AQ_25G_NOT_PRESENT		0X01
> +#define I40E_AQ_25G_NVM_CRC_ERR		0X02
> +#define I40E_AQ_25G_SBUS_UCODE_ERR	0X03
> +#define I40E_AQ_25G_SERDES_UCODE_ERR	0X04
> +#define I40E_AQ_25G_NIMB_UCODE_ERR	0X05
>   	u8	loopback; /* use defines from i40e_aqc_set_lb_mode */
>   	__le16	max_frame_size;
>   	u8	config;
> diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c
> index d1dcd4f..3961fc2 100644
> --- a/drivers/net/ethernet/intel/i40e/i40e_common.c
> +++ b/drivers/net/ethernet/intel/i40e/i40e_common.c
> @@ -53,6 +53,8 @@ static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
>   		case I40E_DEV_ID_10G_BASE_T4:
>   		case I40E_DEV_ID_20G_KR2:
>   		case I40E_DEV_ID_20G_KR2_A:
> +		case I40E_DEV_ID_25G_B:
> +		case I40E_DEV_ID_25G_SFP28:
>   			hw->mac.type = I40E_MAC_XL710;
>   			break;
>   		case I40E_DEV_ID_KX_X722:
> @@ -1183,6 +1185,8 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
>   	case I40E_PHY_TYPE_1000BASE_LX:
>   	case I40E_PHY_TYPE_40GBASE_SR4:
>   	case I40E_PHY_TYPE_40GBASE_LR4:
> +	case I40E_PHY_TYPE_25GBASE_LR:
> +	case I40E_PHY_TYPE_25GBASE_SR:
>   		media = I40E_MEDIA_TYPE_FIBER;
>   		break;
>   	case I40E_PHY_TYPE_100BASE_TX:
> @@ -1197,6 +1201,7 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
>   	case I40E_PHY_TYPE_10GBASE_SFPP_CU:
>   	case I40E_PHY_TYPE_40GBASE_AOC:
>   	case I40E_PHY_TYPE_10GBASE_AOC:
> +	case I40E_PHY_TYPE_25GBASE_CR:
>   		media = I40E_MEDIA_TYPE_DA;
>   		break;
>   	case I40E_PHY_TYPE_1000BASE_KX:
> @@ -1204,6 +1209,7 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
>   	case I40E_PHY_TYPE_10GBASE_KR:
>   	case I40E_PHY_TYPE_40GBASE_KR4:
>   	case I40E_PHY_TYPE_20GBASE_KR2:
> +	case I40E_PHY_TYPE_25GBASE_KR:
>   		media = I40E_MEDIA_TYPE_BACKPLANE;
>   		break;
>   	case I40E_PHY_TYPE_SGMII:
> @@ -1608,8 +1614,10 @@ i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
>   	if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
>   		status = I40E_ERR_UNKNOWN_PHY;
>   
> -	if (report_init)
> +	if (report_init) {
>   		hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
> +		hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
> +	}
>   
>   	return status;
>   }
> @@ -1701,6 +1709,7 @@ enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
>   			config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
>   		/* Copy over all the old settings */
>   		config.phy_type = abilities.phy_type;
> +		config.phy_type_ext = abilities.phy_type_ext;
>   		config.link_speed = abilities.link_speed;
>   		config.eee_capability = abilities.eee_capability;
>   		config.eeer = abilities.eeer_val;
> diff --git a/drivers/net/ethernet/intel/i40e/i40e_devids.h b/drivers/net/ethernet/intel/i40e/i40e_devids.h
> index dd4457d..8e46098 100644
> --- a/drivers/net/ethernet/intel/i40e/i40e_devids.h
> +++ b/drivers/net/ethernet/intel/i40e/i40e_devids.h
> @@ -39,6 +39,8 @@
>   #define I40E_DEV_ID_20G_KR2		0x1587
>   #define I40E_DEV_ID_20G_KR2_A		0x1588
>   #define I40E_DEV_ID_10G_BASE_T4		0x1589
> +#define I40E_DEV_ID_25G_B		0x158A
> +#define I40E_DEV_ID_25G_SFP28		0x158B
>   #define I40E_DEV_ID_KX_X722		0x37CE
>   #define I40E_DEV_ID_QSFP_X722		0x37CF
>   #define I40E_DEV_ID_SFP_X722		0x37D0
> diff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
> index 6ba0035..4b3a71a 100644
> --- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
> +++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
> @@ -265,8 +265,9 @@ static void i40e_partition_setting_complaint(struct i40e_pf *pf)
>   static void i40e_phy_type_to_ethtool(struct i40e_pf *pf, u32 *supported,
>   				     u32 *advertising)
>   {
> -	enum i40e_aq_capabilities_phy_type phy_types = pf->hw.phy.phy_types;
>   	struct i40e_link_status *hw_link_info = &pf->hw.phy.link_info;
> +	u64 phy_types = pf->hw.phy.phy_types;
> +
>   	*supported = 0x0;
>   	*advertising = 0x0;
>   
> @@ -369,6 +370,15 @@ static void i40e_phy_type_to_ethtool(struct i40e_pf *pf, u32 *supported,
>   			if (!(pf->flags & I40E_FLAG_HAVE_CRT_RETIMER))
>   				*advertising |= ADVERTISED_1000baseKX_Full;
>   	}
> +	if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR ||
> +	    phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR ||
> +	    phy_types & I40E_CAP_PHY_TYPE_25GBASE_SR ||
> +	    phy_types & I40E_CAP_PHY_TYPE_25GBASE_LR) {
> +		*supported |= SUPPORTED_Autoneg |
> +			     SUPPORTED_2500baseX_Full;
> +		*advertising |= ADVERTISED_Autoneg |
> +			       ADVERTISED_2500baseX_Full;
> +	}
>   }
>   
>   /**
> @@ -491,6 +501,14 @@ static void i40e_get_settings_link_up(struct i40e_hw *hw,
>   				     ADVERTISED_1000baseKX_Full |
>   				     ADVERTISED_Autoneg;
>   		break;
> +	case I40E_PHY_TYPE_25GBASE_KR:
> +	case I40E_PHY_TYPE_25GBASE_CR:
> +	case I40E_PHY_TYPE_25GBASE_SR:
> +	case I40E_PHY_TYPE_25GBASE_LR:
> +		ecmd->supported |= SUPPORTED_2500baseX_Full |
> +				   SUPPORTED_Autoneg;
> +		ecmd->advertising |= ADVERTISED_2500baseX_Full |
> +				     ADVERTISED_Autoneg;
>   	default:
>   		/* if we got here and link is up something bad is afoot */
>   		netdev_info(netdev, "WARNING: Link is up but PHY type 0x%x is not recognized.\n",
> diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
> index a032dfd..849feaa 100644
> --- a/drivers/net/ethernet/intel/i40e/i40e_main.c
> +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
> @@ -86,6 +86,8 @@ static const struct pci_device_id i40e_pci_tbl[] = {
>   	{PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0},
>   	{PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
>   	{PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
> +	{PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_B), 0},
> +	{PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_SFP28), 0},
>   	/* required last entry */
>   	{0, }
>   };
> @@ -5248,6 +5250,9 @@ void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
>   	case I40E_LINK_SPEED_20GB:
>   		speed = "20 G";
>   		break;
> +	case I40E_LINK_SPEED_25GB:
> +		speed = "25 G";
> +		break;
>   	case I40E_LINK_SPEED_10GB:
>   		speed = "10 G";
>   		break;
> @@ -11356,7 +11361,6 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>   		dev_dbg(&pf->pdev->dev, "get supported phy types ret =  %s last_status =  %s\n",
>   			i40e_stat_str(&pf->hw, err),
>   			i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
> -	pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
>   
>   	/* Add a filter to drop all Flow control frames from any VSI from being
>   	 * transmitted. By doing so we stop a malicious VF from sending out
> diff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h
> index e02cb73..7272be3 100644
> --- a/drivers/net/ethernet/intel/i40e/i40e_type.h
> +++ b/drivers/net/ethernet/intel/i40e/i40e_type.h
> @@ -213,47 +213,59 @@ struct i40e_link_status {
>   #define I40E_MODULE_TYPE_1000BASE_T	0x08
>   };
>   
> -enum i40e_aq_capabilities_phy_type {
> -	I40E_CAP_PHY_TYPE_SGMII		  = BIT(I40E_PHY_TYPE_SGMII),
> -	I40E_CAP_PHY_TYPE_1000BASE_KX	  = BIT(I40E_PHY_TYPE_1000BASE_KX),
> -	I40E_CAP_PHY_TYPE_10GBASE_KX4	  = BIT(I40E_PHY_TYPE_10GBASE_KX4),
> -	I40E_CAP_PHY_TYPE_10GBASE_KR	  = BIT(I40E_PHY_TYPE_10GBASE_KR),
> -	I40E_CAP_PHY_TYPE_40GBASE_KR4	  = BIT(I40E_PHY_TYPE_40GBASE_KR4),
> -	I40E_CAP_PHY_TYPE_XAUI		  = BIT(I40E_PHY_TYPE_XAUI),
> -	I40E_CAP_PHY_TYPE_XFI		  = BIT(I40E_PHY_TYPE_XFI),
> -	I40E_CAP_PHY_TYPE_SFI		  = BIT(I40E_PHY_TYPE_SFI),
> -	I40E_CAP_PHY_TYPE_XLAUI		  = BIT(I40E_PHY_TYPE_XLAUI),
> -	I40E_CAP_PHY_TYPE_XLPPI		  = BIT(I40E_PHY_TYPE_XLPPI),
> -	I40E_CAP_PHY_TYPE_40GBASE_CR4_CU  = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
> -	I40E_CAP_PHY_TYPE_10GBASE_CR1_CU  = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
> -	I40E_CAP_PHY_TYPE_10GBASE_AOC	  = BIT(I40E_PHY_TYPE_10GBASE_AOC),
> -	I40E_CAP_PHY_TYPE_40GBASE_AOC	  = BIT(I40E_PHY_TYPE_40GBASE_AOC),
> -	I40E_CAP_PHY_TYPE_100BASE_TX	  = BIT(I40E_PHY_TYPE_100BASE_TX),
> -	I40E_CAP_PHY_TYPE_1000BASE_T	  = BIT(I40E_PHY_TYPE_1000BASE_T),
> -	I40E_CAP_PHY_TYPE_10GBASE_T	  = BIT(I40E_PHY_TYPE_10GBASE_T),
> -	I40E_CAP_PHY_TYPE_10GBASE_SR	  = BIT(I40E_PHY_TYPE_10GBASE_SR),
> -	I40E_CAP_PHY_TYPE_10GBASE_LR	  = BIT(I40E_PHY_TYPE_10GBASE_LR),
> -	I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
> -	I40E_CAP_PHY_TYPE_10GBASE_CR1	  = BIT(I40E_PHY_TYPE_10GBASE_CR1),
> -	I40E_CAP_PHY_TYPE_40GBASE_CR4	  = BIT(I40E_PHY_TYPE_40GBASE_CR4),
> -	I40E_CAP_PHY_TYPE_40GBASE_SR4	  = BIT(I40E_PHY_TYPE_40GBASE_SR4),
> -	I40E_CAP_PHY_TYPE_40GBASE_LR4	  = BIT(I40E_PHY_TYPE_40GBASE_LR4),
> -	I40E_CAP_PHY_TYPE_1000BASE_SX	  = BIT(I40E_PHY_TYPE_1000BASE_SX),
> -	I40E_CAP_PHY_TYPE_1000BASE_LX	  = BIT(I40E_PHY_TYPE_1000BASE_LX),
> -	I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL =
> -					 BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
> -	I40E_CAP_PHY_TYPE_20GBASE_KR2	  = BIT(I40E_PHY_TYPE_20GBASE_KR2)
> -};
> -
>   struct i40e_phy_info {
>   	struct i40e_link_status link_info;
>   	struct i40e_link_status link_info_old;
>   	bool get_link_info;
>   	enum i40e_media_type media_type;
>   	/* all the phy types the NVM is capable of */
> -	enum i40e_aq_capabilities_phy_type phy_types;
> -};
> -
> +	u64 phy_types;
> +};
> +
> +#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
> +#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
> +#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
> +#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
> +#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
> +#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
> +#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
> +#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
> +#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
> +#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
> +#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
> +#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
> +#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
> +#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
> +#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
> +#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
> +#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
> +#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
> +#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
> +#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
> +#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
> +#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
> +#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
> +#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
> +#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
> +#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
> +#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
> +				BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
> +#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
> +/* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
> + * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
> + * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
> + * a shift is needed to adjust for this with values larger than 31. The
> + * only affected values are I40E_PHY_TYPE_25GBASE_*.
> + */
> +#define I40E_PHY_TYPE_OFFSET 1
> +#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
> +					     I40E_PHY_TYPE_OFFSET)
> +#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
> +					     I40E_PHY_TYPE_OFFSET)
> +#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
> +					     I40E_PHY_TYPE_OFFSET)
> +#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
> +					     I40E_PHY_TYPE_OFFSET)
>   #define I40E_HW_CAP_MAX_GPIO			30
>   /* Capabilities of a PF or a VF or the whole device */
>   struct i40e_hw_capabilities {
> diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
> index 05ed49b..d28b684 100644
> --- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
> +++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
> @@ -2921,6 +2921,9 @@ int i40e_ndo_set_vf_bw(struct net_device *netdev, int vf_id, int min_tx_rate,
>   	case I40E_LINK_SPEED_40GB:
>   		speed = 40000;
>   		break;
> +	case I40E_LINK_SPEED_25GB:
> +		speed = 25000;
> +		break;
>   	case I40E_LINK_SPEED_20GB:
>   		speed = 20000;
>   		break;
> diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h
> index 40b0eaf..f8d7d95 100644
> --- a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h
> +++ b/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h
> @@ -1639,6 +1639,10 @@ enum i40e_aq_phy_type {
>   	I40E_PHY_TYPE_1000BASE_LX		= 0x1C,
>   	I40E_PHY_TYPE_1000BASE_T_OPTICAL	= 0x1D,
>   	I40E_PHY_TYPE_20GBASE_KR2		= 0x1E,
> +	I40E_PHY_TYPE_25GBASE_KR		= 0x1F,
> +	I40E_PHY_TYPE_25GBASE_CR		= 0x20,
> +	I40E_PHY_TYPE_25GBASE_SR		= 0x21,
> +	I40E_PHY_TYPE_25GBASE_LR		= 0x22,
>   	I40E_PHY_TYPE_MAX
>   };
>   
> @@ -1647,6 +1651,7 @@ enum i40e_aq_phy_type {
>   #define I40E_LINK_SPEED_10GB_SHIFT	0x3
>   #define I40E_LINK_SPEED_40GB_SHIFT	0x4
>   #define I40E_LINK_SPEED_20GB_SHIFT	0x5
> +#define I40E_LINK_SPEED_25GB_SHIFT	0x6
>   
>   enum i40e_aq_link_speed {
>   	I40E_LINK_SPEED_UNKNOWN	= 0,
> @@ -1654,7 +1659,8 @@ enum i40e_aq_link_speed {
>   	I40E_LINK_SPEED_1GB	= BIT(I40E_LINK_SPEED_1000MB_SHIFT),
>   	I40E_LINK_SPEED_10GB	= BIT(I40E_LINK_SPEED_10GB_SHIFT),
>   	I40E_LINK_SPEED_40GB	= BIT(I40E_LINK_SPEED_40GB_SHIFT),
> -	I40E_LINK_SPEED_20GB	= BIT(I40E_LINK_SPEED_20GB_SHIFT)
> +	I40E_LINK_SPEED_20GB	= BIT(I40E_LINK_SPEED_20GB_SHIFT),
> +	I40E_LINK_SPEED_25GB	= BIT(I40E_LINK_SPEED_25GB_SHIFT),
>   };
>   
>   struct i40e_aqc_module_desc {
> @@ -1687,7 +1693,13 @@ struct i40e_aq_get_phy_abilities_resp {
>   	__le32	eeer_val;
>   	u8	d3_lpan;
>   #define I40E_AQ_SET_PHY_D3_LPAN_ENA	0x01
> -	u8	reserved[3];
> +	u8	phy_type_ext;
> +#define I40E_AQ_PHY_TYPE_EXT_25G_KR	0X01
> +#define I40E_AQ_PHY_TYPE_EXT_25G_CR	0X02
> +#define I40E_AQ_PHY_TYPE_EXT_25G_SR	0x04
> +#define I40E_AQ_PHY_TYPE_EXT_25G_LR	0x08
> +	u8	mod_type_ext;
> +	u8	ext_comp_code;
>   	u8	phy_id[4];
>   	u8	module_type[3];
>   	u8	qualified_module_count;
> @@ -1709,7 +1721,12 @@ struct i40e_aq_set_phy_config { /* same bits as above in all */
>   	__le16	eee_capability;
>   	__le32	eeer;
>   	u8	low_power_ctrl;
> -	u8	reserved[3];
> +	u8	phy_type_ext;
> +#define I40E_AQ_PHY_TYPE_EXT_25G_KR	0X01
> +#define I40E_AQ_PHY_TYPE_EXT_25G_CR	0X02
> +#define I40E_AQ_PHY_TYPE_EXT_25G_SR	0x04
> +#define I40E_AQ_PHY_TYPE_EXT_25G_LR	0x08
> +	u8	reserved[2];
>   };
>   
>   I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
> @@ -1789,6 +1806,13 @@ struct i40e_aqc_get_link_status {
>   #define I40E_AQ_LINK_TX_DRAINED		0x01
>   #define I40E_AQ_LINK_TX_FLUSHED		0x03
>   #define I40E_AQ_LINK_FORCED_40G		0x10
> +/* 25G Error Codes */
> +#define I40E_AQ_25G_NO_ERR		0X00
> +#define I40E_AQ_25G_NOT_PRESENT		0X01
> +#define I40E_AQ_25G_NVM_CRC_ERR		0X02
> +#define I40E_AQ_25G_SBUS_UCODE_ERR	0X03
> +#define I40E_AQ_25G_SERDES_UCODE_ERR	0X04
> +#define I40E_AQ_25G_NIMB_UCODE_ERR	0X05
>   	u8	loopback; /* use defines from i40e_aqc_set_lb_mode */
>   	__le16	max_frame_size;
>   	u8	config;
> diff --git a/drivers/net/ethernet/intel/i40evf/i40e_common.c b/drivers/net/ethernet/intel/i40evf/i40e_common.c
> index 7953c13..aa63b7f 100644
> --- a/drivers/net/ethernet/intel/i40evf/i40e_common.c
> +++ b/drivers/net/ethernet/intel/i40evf/i40e_common.c
> @@ -53,6 +53,8 @@ i40e_status i40e_set_mac_type(struct i40e_hw *hw)
>   		case I40E_DEV_ID_10G_BASE_T4:
>   		case I40E_DEV_ID_20G_KR2:
>   		case I40E_DEV_ID_20G_KR2_A:
> +		case I40E_DEV_ID_25G_B:
> +		case I40E_DEV_ID_25G_SFP28:
>   			hw->mac.type = I40E_MAC_XL710;
>   			break;
>   		case I40E_DEV_ID_SFP_X722:
> diff --git a/drivers/net/ethernet/intel/i40evf/i40e_devids.h b/drivers/net/ethernet/intel/i40evf/i40e_devids.h
> index 7023570..21dcaee 100644
> --- a/drivers/net/ethernet/intel/i40evf/i40e_devids.h
> +++ b/drivers/net/ethernet/intel/i40evf/i40e_devids.h
> @@ -39,6 +39,8 @@
>   #define I40E_DEV_ID_20G_KR2		0x1587
>   #define I40E_DEV_ID_20G_KR2_A		0x1588
>   #define I40E_DEV_ID_10G_BASE_T4		0x1589
> +#define I40E_DEV_ID_25G_B		0x158A
> +#define I40E_DEV_ID_25G_SFP28		0x158B
>   #define I40E_DEV_ID_VF			0x154C
>   #define I40E_DEV_ID_VF_HV		0x1571
>   #define I40E_DEV_ID_SFP_X722		0x37D0
> diff --git a/drivers/net/ethernet/intel/i40evf/i40e_type.h b/drivers/net/ethernet/intel/i40evf/i40e_type.h
> index 515484c..c85e8a3 100644
> --- a/drivers/net/ethernet/intel/i40evf/i40e_type.h
> +++ b/drivers/net/ethernet/intel/i40evf/i40e_type.h
> @@ -187,47 +187,59 @@ struct i40e_link_status {
>   #define I40E_MODULE_TYPE_1000BASE_T	0x08
>   };
>   
> -enum i40e_aq_capabilities_phy_type {
> -	I40E_CAP_PHY_TYPE_SGMII		  = BIT(I40E_PHY_TYPE_SGMII),
> -	I40E_CAP_PHY_TYPE_1000BASE_KX	  = BIT(I40E_PHY_TYPE_1000BASE_KX),
> -	I40E_CAP_PHY_TYPE_10GBASE_KX4	  = BIT(I40E_PHY_TYPE_10GBASE_KX4),
> -	I40E_CAP_PHY_TYPE_10GBASE_KR	  = BIT(I40E_PHY_TYPE_10GBASE_KR),
> -	I40E_CAP_PHY_TYPE_40GBASE_KR4	  = BIT(I40E_PHY_TYPE_40GBASE_KR4),
> -	I40E_CAP_PHY_TYPE_XAUI		  = BIT(I40E_PHY_TYPE_XAUI),
> -	I40E_CAP_PHY_TYPE_XFI		  = BIT(I40E_PHY_TYPE_XFI),
> -	I40E_CAP_PHY_TYPE_SFI		  = BIT(I40E_PHY_TYPE_SFI),
> -	I40E_CAP_PHY_TYPE_XLAUI		  = BIT(I40E_PHY_TYPE_XLAUI),
> -	I40E_CAP_PHY_TYPE_XLPPI		  = BIT(I40E_PHY_TYPE_XLPPI),
> -	I40E_CAP_PHY_TYPE_40GBASE_CR4_CU  = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
> -	I40E_CAP_PHY_TYPE_10GBASE_CR1_CU  = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
> -	I40E_CAP_PHY_TYPE_10GBASE_AOC	  = BIT(I40E_PHY_TYPE_10GBASE_AOC),
> -	I40E_CAP_PHY_TYPE_40GBASE_AOC	  = BIT(I40E_PHY_TYPE_40GBASE_AOC),
> -	I40E_CAP_PHY_TYPE_100BASE_TX	  = BIT(I40E_PHY_TYPE_100BASE_TX),
> -	I40E_CAP_PHY_TYPE_1000BASE_T	  = BIT(I40E_PHY_TYPE_1000BASE_T),
> -	I40E_CAP_PHY_TYPE_10GBASE_T	  = BIT(I40E_PHY_TYPE_10GBASE_T),
> -	I40E_CAP_PHY_TYPE_10GBASE_SR	  = BIT(I40E_PHY_TYPE_10GBASE_SR),
> -	I40E_CAP_PHY_TYPE_10GBASE_LR	  = BIT(I40E_PHY_TYPE_10GBASE_LR),
> -	I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
> -	I40E_CAP_PHY_TYPE_10GBASE_CR1	  = BIT(I40E_PHY_TYPE_10GBASE_CR1),
> -	I40E_CAP_PHY_TYPE_40GBASE_CR4	  = BIT(I40E_PHY_TYPE_40GBASE_CR4),
> -	I40E_CAP_PHY_TYPE_40GBASE_SR4	  = BIT(I40E_PHY_TYPE_40GBASE_SR4),
> -	I40E_CAP_PHY_TYPE_40GBASE_LR4	  = BIT(I40E_PHY_TYPE_40GBASE_LR4),
> -	I40E_CAP_PHY_TYPE_1000BASE_SX	  = BIT(I40E_PHY_TYPE_1000BASE_SX),
> -	I40E_CAP_PHY_TYPE_1000BASE_LX	  = BIT(I40E_PHY_TYPE_1000BASE_LX),
> -	I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL =
> -					 BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
> -	I40E_CAP_PHY_TYPE_20GBASE_KR2	  = BIT(I40E_PHY_TYPE_20GBASE_KR2)
> -};
> -
>   struct i40e_phy_info {
>   	struct i40e_link_status link_info;
>   	struct i40e_link_status link_info_old;
>   	bool get_link_info;
>   	enum i40e_media_type media_type;
>   	/* all the phy types the NVM is capable of */
> -	enum i40e_aq_capabilities_phy_type phy_types;
> -};
> -
> +	u64 phy_types;
> +};
> +
> +#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
> +#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
> +#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
> +#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
> +#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
> +#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
> +#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
> +#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
> +#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
> +#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
> +#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
> +#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
> +#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
> +#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
> +#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
> +#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
> +#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
> +#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
> +#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
> +#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
> +#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
> +#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
> +#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
> +#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
> +#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
> +#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
> +#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
> +				BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
> +#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
> +/* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
> + * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
> + * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
> + * a shift is needed to adjust for this with values larger than 31. The
> + * only affected values are I40E_PHY_TYPE_25GBASE_*.
> + */
> +#define I40E_PHY_TYPE_OFFSET 1
> +#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
> +					     I40E_PHY_TYPE_OFFSET)
> +#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
> +					     I40E_PHY_TYPE_OFFSET)
> +#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
> +					     I40E_PHY_TYPE_OFFSET)
> +#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
> +					     I40E_PHY_TYPE_OFFSET)
>   #define I40E_HW_CAP_MAX_GPIO			30
>   /* Capabilities of a PF or a VF or the whole device */
>   struct i40e_hw_capabilities {
> diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c b/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c
> index a994015..272d600 100644
> --- a/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c
> +++ b/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c
> @@ -85,6 +85,14 @@ static int i40evf_get_settings(struct net_device *netdev,
>   	case I40E_LINK_SPEED_40GB:
>   		ethtool_cmd_speed_set(ecmd, SPEED_40000);
>   		break;
> +	case I40E_LINK_SPEED_25GB:
> +#ifdef SPEED_25000
> +		ethtool_cmd_speed_set(ecmd, SPEED_25000);
> +#else
> +		netdev_info(netdev,
> +			    "Speed is 25G, display not supported by this version of ethtool.\n");
> +#endif
> +		break;
>   	case I40E_LINK_SPEED_20GB:
>   		ethtool_cmd_speed_set(ecmd, SPEED_20000);
>   		break;
> diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c b/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c
> index ddf478d..2059a8e 100644
> --- a/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c
> +++ b/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c
> @@ -836,6 +836,9 @@ static void i40evf_print_link_message(struct i40evf_adapter *adapter)
>   	case I40E_LINK_SPEED_40GB:
>   		speed = "40 G";
>   		break;
> +	case I40E_LINK_SPEED_25GB:
> +		speed = "25 G";
> +		break;
>   	case I40E_LINK_SPEED_20GB:
>   		speed = "20 G";
>   		break;



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