[Intel-wired-lan] [next PATCH S72-V3 12/13] i40e: Handle PE_CRITERR properly with IWARP enabled

Bowers, AndrewX andrewx.bowers at intel.com
Mon Jun 12 18:14:32 UTC 2017


> -----Original Message-----
> From: Intel-wired-lan [mailto:intel-wired-lan-bounces at osuosl.org] On
> Behalf Of Alice Michael
> Sent: Wednesday, June 7, 2017 2:43 AM
> To: Michael, Alice <alice.michael at intel.com>; intel-wired-
> lan at lists.osuosl.org
> Cc: Catherine Sullivan <catherine.sullivan at intel.com>
> Subject: [Intel-wired-lan] [next PATCH S72-V3 12/13] i40e: Handle
> PE_CRITERR properly with IWARP enabled
> 
> From: Catherine Sullivan <catherine.sullivan at intel.com>
> 
> When IWARP is enabled, we weren't clearing the PE_CRITERR, just logging it
> and removing it from the mask. We need to do a corer to reset the
> PE_CRITERR register, so set the bit for that as we handle the interrupt.
> 
> We should also be checking for the error against the PFINT_ICR0 register, and
> only need to clear it in the value getting written to PFINT_ICR0_ENA.
> 
> Signed-off-by: Catherine Sullivan <catherine.sullivan at intel.com>
> Signed-off-by: Mitch Williams <mitch.a.williams at intel.com>
> ---
>  drivers/net/ethernet/intel/i40e/i40e_main.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Tested-by: Andrew Bowers <andrewx.bowers at intel.com>




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