[Intel-wired-lan] [PATCH v3 06/16] fm10k: simplify reading PFVFLRE register

Singh, Krishneil K krishneil.k.singh at intel.com
Mon Sep 18 17:09:37 UTC 2017


> -----Original Message-----
> From: Intel-wired-lan [mailto:intel-wired-lan-bounces at osuosl.org] On Behalf
> Of Jacob Keller
> Sent: Monday, July 10, 2017 1:23 PM
> To: jtkirhse at osuosl.org; Intel Wired LAN <intel-wired-lan at lists.osuosl.org>
> Cc: jekeller at osuosl.org
> Subject: [Intel-wired-lan] [PATCH v3 06/16] fm10k: simplify reading PFVFLRE
> register
> 
> We're doing a really convoluted bitshift and read for the PFVFLRE
> register. Just reading the PFVFLRE(1), shifting it by 32, then reading
> PFVFLRE(0) should be sufficient.
> 
> Signed-off-by: Jacob Keller <jacob.e.keller at intel.com>
> ---

Tested-by: Krishneil Singh  <krishneil.k.singh at intel.com>



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