[Intel-wired-lan] [PATCH v6 02/11] igc: Add support for PF

Neftin, Sasha sasha.neftin at intel.com
Mon Aug 27 07:04:18 UTC 2018


On 8/23/2018 19:37, Shannon Nelson wrote:
> On 8/23/2018 12:05 AM, Sasha Neftin wrote:
> 
> [...]
> 
>> +#define array_wr32(reg, offset, value) \
>> +    wr32((reg) + ((offset) << 2), (value))
>> +
>> +#define array_rd32(reg, offset) (igc_rd32(hw, (reg) + ((offset) << 2)))
>> +
> 
> Hmm... you may want to be careful with these array defines.  I don't 
> know what the register set looks like, but on some devices I've seen 
> array element offset is in things like 128 byte chunks rather than 
> 4-byte words.
> 
> sln
> 
Good point. We use this define for read array of 32 bit registers. Also, 
I will add validation request to double check how it work.
Thanks,
Sasha


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