[Intel-wired-lan] [RFC net-next 1/7] ptp: Add interface for acquiring DPLL state

Machnikowski, Maciej maciej.machnikowski at intel.com
Fri Aug 20 18:30:02 UTC 2021

> -----Original Message-----
> From: Richard Cochran <richardcochran at gmail.com>
> Sent: Friday, August 20, 2021 5:56 PM
> To: Machnikowski, Maciej <maciej.machnikowski at intel.com>
> Cc: Kubalewski, Arkadiusz <arkadiusz.kubalewski at intel.com>; linux-
> kernel at vger.kernel.org; intel-wired-lan at lists.osuosl.org;
> netdev at vger.kernel.org; linux-kselftest at vger.kernel.org; Brandeburg,
> Jesse <jesse.brandeburg at intel.com>; Nguyen, Anthony L
> <anthony.l.nguyen at intel.com>; davem at davemloft.net; kuba at kernel.org;
> shuah at kernel.org; arnd at arndb.de; nikolay at nvidia.com;
> cong.wang at bytedance.com; colin.king at canonical.com;
> gustavoars at kernel.org; Bross, Kevin <kevin.bross at intel.com>; Stanton,
> Kevin B <kevin.b.stanton at intel.com>; Ahmad Byagowi <abyagowi at fb.com>
> Subject: Re: [RFC net-next 1/7] ptp: Add interface for acquiring DPLL state
> 1. Control bits according to IEEE 802.3 Section 40.5.2 as Ethtool or RTNL.
> 2. User space Ethernet Synchronization Messaging Channel (ESMC)
>    service according to IEEE 802.3ay
> The PHY should be automatically controlled by #1.
> As I said before, none of this belongs in the PHC subsystem.
> Thanks,
> Richard


I did a talk at netDev 0x15 covering SyncE - you can refer to the slides for more detailed info, and hopefully the recording will be available soon as well:

At its core - SyncE requires 2 parts (see slide 22/23)
 - SyncE capable PHY
 - the external DPLL

The SyncE capable PHY is a PHY that can recover the physical clock, at which the data symbols are transferred, (usually) divide it and output it to the external PLL. It can also redirect the recovered and divided clock to more than one pin.
Since the 40.5.2 is not applicable to higher-speed ethernet which don't use auto-negotiation, but rather the link training sequence where the RX side always syncs its clock to the TX side.

The external DPLL tunes the frequency generated by a crystal to the frequency recovered by the PHY, and drives the outputs.

On the other end - the SyncE PHY uses the clock generated by the DPLL to transmit the data to the next element.

So to be able to control SyncE we need 2 interfaces:
- Interface to enable the recovered clock output at the given pin
- interface to monitor the DPLL to see if the clock that we got is valid, or not.

If it comes to ESMC (G.8264) messages, SyncE itself can run in 2 modes (slides 29/30 will give you more details):
- QL-Disabled - with no ESMC messages - it base on the local information from the PLL to make all decisions
- QL-Enabled - that adds ESMC and quality message transfer between the nodes.

Additionally, the SyncE DPLL can be synchronized to the external sources, like a 1PPS or a 10M signal from the GNSS.

That's why the RFC proposes 2 interfaces:
- one for enabling redirected clock on a selected pin of the PHY
- one for the physical frequency lock of the DPLL

The connection with the PTP subsystem is that in most use cases I heard about SyncE is used as a physical frequency syntonization for PTP clocks.
Hence adding a DPLL monitoring there would solve 2 issues at the same time - monitoring of a GNSS-syntonized PTP clock and the SyncE syntonized one and would make a single point to monitor by the upper layer applications.

Let me know if that makes more sense now. We could add a separate SyncE and separate PTP DPLL monitoring interfaces, but in most cases they will point to the same device.


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