[Intel-wired-lan] [PATCH net v1] ice: Fix PTP TX timestamp offset calculation

[G, GurucharanX]

> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces at osuosl.org> On Behalf Of
> Michal Michalik
> Sent: Tuesday, May 10, 2022 4:34 PM
> To: intel-wired-lan at lists.osuosl.org
> Subject: [Intel-wired-lan] [PATCH net v1] ice: Fix PTP TX timestamp offset
> calculation
> 
> The offset was being incorrectly calculated for E822 - that led to collisions in
> choosing TX timestamp register location when more than one port was trying
> to use timestamping mechanism.
> 
> In E822 one quad is being logically split between ports, so quad 0 is having
> trackers for ports 0-3, quad 1 ports 4-7 etc. Each port should have separate
> memory location for tracking timestamps. Due to error for example ports 1
> and 2 had been assigned to quad 0 with same offset (0), while port 1 should
> have offset 0 and 1 offset 16.
> 
> Fix it by correctly calculating quad offset.
> 
> Fixes: 3a7496234d17 ("ice: implement basic E822 PTP support")
> Signed-off-by: Michal Michalik <michal.michalik at intel.com>
> ---
>  drivers/net/ethernet/intel/ice/ice_ptp.c |  2 +-
> drivers/net/ethernet/intel/ice/ice_ptp.h | 30
> ++++++++++++++++++++++++++++++
>  2 files changed, 31 insertions(+), 1 deletion(-)
> 

Tested-by: Gurucharan <gurucharanx.g at intel.com> (A Contingent worker at Intel)