[Intel-wired-lan] [PATCH 1/1] ice: restrict PTP HW clock freq adjustments to 100, 000, 000 PPB

[G, GurucharanX]

> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces at osuosl.org> On Behalf Of
> Siddaraju DH
> Sent: Tuesday, November 15, 2022 3:12 PM
> To: intel-wired-lan at lists.osuosl.org
> Cc: D H, Siddaraju <siddaraju.dh at intel.com>
> Subject: [Intel-wired-lan] [PATCH 1/1] ice: restrict PTP HW clock freq
> adjustments to 100, 000, 000 PPB
> 
> The PHY provides only 39b timestamp. With current timing implementation,
> we discard lower 7b, leaving 32b timestamp.
> The driver reconstructs the full 64b timestamp by correlating the 32b
> timestamp with cached_time for performance. The reconstruction algorithm
> does both forward & backward interpolation.
> 
> The 32b timeval has overflow duration of 2^32 counts ~= 4.23 second.
> Due to interpolation in both direction, its now ~= 2.125 second IIRC, going
> with at least half a duration, the cached_time is updated with periodic thread
> of 1 second (worst-case) periodicity.
> 
> But the 1 second periodicity is based on System-timer.
> With PPB adjustments, if the 1588 timers increments at say double the rate,
> (2s in-place of 1s), the Nyquist rate/half duration sampling/update of
> cached_time with 1 second periodic thread will lead to incorrect
> interpolations.
> 
> Hence we should restrict the PPB adjustments to at least half duration of
> cached_time update which translates to 500,000,000 PPB.
> 
> Since the periodicity of the cached-time system thread can vary, it is good to
> have some buffer time and considering practicality of PPB adjustments,
> limiting the max_adj to 100,000,000.
> 
> Signed-off-by: Siddaraju DH <siddaraju.dh at intel.com>
> ---
>  drivers/net/ethernet/intel/ice/ice_ptp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Tested-by: Gurucharan G <gurucharanx.g at intel.com> (A Contingent worker at Intel)