[Intel-wired-lan] [PATCH] igc: fix the validation logic for taprio's gate list

[Vinicius Costa Gomes]

Kurt Kanzenbach <kurt at linutronix.de> writes:

> On Tue Mar 07 2023, AKASHI Takahiro wrote:
>> The check introduced in the commit a5fd39464a40 ("igc: Lift TAPRIO schedule
>> restriction") can detect a false positive error in some corner case.
>> For instance,
>>     tc qdisc replace ... taprio num_tc 4
>> 	...
>> 	sched-entry S 0x01 100000	# slot#1
>> 	sched-entry S 0x03 100000	# slot#2
>> 	sched-entry S 0x04 100000	# slot#3
>> 	sched-entry S 0x08 200000	# slot#4
>> 	flags 0x02			# hardware offload
>>
>> Here the queue#0 (the first queue) is on at the slot#1 and #2,
>> and off at the slot#3 and #4. Under the current logic, when the slot#4
>> is examined, validate_schedule() returns *false* since the enablement
>> count for the queue#0 is two and it is already off at the previous slot
>> (i.e. #3). But this definition is truely correct.
>>
>> Let's fix the logic to enforce a strict validation for consecutively-opened
>> slots.
>>
>> Fixes: a5fd39464a40 ("igc: Lift TAPRIO schedule restriction")
>> Signed-off-by: AKASHI Takahiro <takahiro.akashi at linaro.org>
>
> Grml. Thanks!
>
> Reviewed-by: Kurt Kanzenbach <kurt at linutronix.de>

Acked-by: Vinicius Costa Gomes <vinicius.gomes at intel.com>


Cheers,
-- 
Vinicius