[Intel-wired-lan] [PATCH iwl-next v2 1/3] ice: PTP: Clean up timestamp registers correctly
Pucha, HimasekharX Reddy
himasekharx.reddy.pucha at intel.com
Mon Aug 28 09:59:16 UTC 2023
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces at osuosl.org> On Behalf Of Jacob Keller
> Sent: Wednesday, July 26, 2023 11:58 PM
> To: Intel Wired LAN <intel-wired-lan at lists.osuosl.org>
> Cc: Paul Menzel <pmenzel at molgen.mpg.de>; Kolacinski, Karol <karol.kolacinski at intel.com>; Nguyen, Anthony L <anthony.l.nguyen at intel.com>
> Subject: [Intel-wired-lan] [PATCH iwl-next v2 1/3] ice: PTP: Clean up timestamp registers correctly
>
> From: Karol Kolacinski <karol.kolacinski at intel.com>
>
> E822 PHY TS registers should not be written and the only way to clean up
> them is to reset QUAD memory.
>
> To ensure that the status bit for the timestamp index is cleared, ensure
> that ice_clear_phy_tstamp implementations first read the timestamp out.
> Implementations which can write the register continue to do so.
>
> Add a note to indicate this function should only be called on timestamps
> which have their valid bit set. Update the dynamic debug messages to
> reflect the actual action taken.
>
> Signed-off-by: Karol Kolacinski <karol.kolacinski at intel.com>
> Signed-off-by: Jacob Keller <jacob.e.keller at intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 70 +++++++++++++--------
> 1 file changed, 45 insertions(+), 25 deletions(-)
>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha at intel.com> (A Contingent worker at Intel)
More information about the Intel-wired-lan
mailing list