[Intel-wired-lan] [PATCH v3 iwl-next 0/7] ice: Cleanup and refactor PTP pin handling
Karol Kolacinski
karol.kolacinski at intel.com
Thu Aug 29 11:28:07 UTC 2024
This series cleans up current PTP GPIO pin handling, fixes minor bugs,
refactors implementation for all products, introduces SDP (Software
Definable Pins) for E825C and implements reading SDP section from NVM
for E810 products.
Karol Kolacinski (5):
ice: Implement ice_ptp_pin_desc
ice: Add SDPs support for E825C
ice: Align E810T GPIO to other products
ice: Cache perout/extts requests and check flags
ice: Disable shared pin on E810 on setfunc
Sergey Temerkhanov (1):
ice: Enable 1PPS out from CGU for E825C products
Yochai Hagvi (1):
ice: Read SDP section from NVM for pin definitions
.../net/ethernet/intel/ice/ice_adminq_cmd.h | 9 +
drivers/net/ethernet/intel/ice/ice_gnss.c | 4 +-
drivers/net/ethernet/intel/ice/ice_ptp.c | 1129 +++++++++--------
drivers/net/ethernet/intel/ice/ice_ptp.h | 119 +-
.../net/ethernet/intel/ice/ice_ptp_consts.h | 2 +-
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 103 +-
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 72 +-
7 files changed, 799 insertions(+), 639 deletions(-)
V2 -> V3: swapped in/out pin numbers in all patches introducing them
V1 -> V2: fixed formatting issues for:
- ice: Implement ice_ptp_pin_desc
- ice: Add SDPs support for E825C
- ice: Align E810T GPIO to other products
- ice: Cache perout/extts requests and check flags
- ice: Disable shared pin on E810 on setfunc
- ice: Enable 1PPS out from CGU for E825C products
base-commit: e3b49a7f2d9eded4f7fa4d4a5c803986d747e192
--
2.46.0
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