[Intel-wired-lan] [PATCH iwl-next v2 1/5] ice: use rd32_poll_timeout_atomic in ice_read_phy_tstamp_ll_e810

Rinitha, SX sx.rinitha at intel.com
Mon Dec 23 17:16:40 UTC 2024


> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces at osuosl.org> On Behalf Of Anton Nadezhdin
> Sent: 16 December 2024 20:23
> To: intel-wired-lan at lists.osuosl.org
> Cc: netdev at vger.kernel.org; Nguyen, Anthony L <anthony.l.nguyen at intel.com>; Kitszel, Przemyslaw <przemyslaw.kitszel at intel.com>; richardcochran at gmail.com; Keller, Jacob E <jacob.e.keller at intel.com>; Kolacinski, Karol <karol.kolacinski at intel.com>; Olech, Milena <milena.olech at intel.com>; Nadezhdin, Anton <anton.nadezhdin at intel.com>
> Subject: [Intel-wired-lan] [PATCH iwl-next v2 1/5] ice: use rd32_poll_timeout_atomic in ice_read_phy_tstamp_ll_e810
>
> From: Jacob Keller <jacob.e.keller at intel.com>
>
> The ice_read_phy_tstamp_ll_e810 function repeatedly reads the PF_SB_ATQBAL register until the TS_LL_READ_TS bit is cleared. This is a perfect candidate for using rd32_poll_timeout. However, the default implementation uses a sleep-based wait.
>
> Add a new rd32_poll_timeout_atomic macro which is based on the non-sleeping read_poll_timeout_atomic implementation. Use this to replace the loop reading in the ice_read_phy_tstamp_ll_e810 function.
>
> This will also be used in the future when low latency PHY timer updates are supported.
>
> Co-developed-by: Karol Kolacinski <karol.kolacinski at intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski at intel.com>
> Signed-off-by: Jacob Keller <jacob.e.keller at intel.com>
> Reviewed-by: Milena Olech <milena.olech at intel.com>
> Signed-off-by: Anton Nadezhdin <anton.nadezhdin at intel.com>
> ---
> drivers/net/ethernet/intel/ice/ice_osdep.h  |  3 +++  drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 30 +++++++++------------  drivers/net/ethernet/intel/ice/ice_ptp_hw.h |  2 +-
> 3 files changed, 17 insertions(+), 18 deletions(-)
>

Tested-by: Rinitha S <sx.rinitha at intel.com> (A Contingent worker at Intel)


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