[Intel-wired-lan] [PATCH net-next 12/12] ice: dpll: Support E825-C SyncE and dynamic pin discovery

[Loktionov, Aleksandr]

> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces at osuosl.org> On Behalf
> Of Ivan Vecera
> Sent: Thursday, January 8, 2026 7:23 PM
> To: netdev at vger.kernel.org
> Cc: Eric Dumazet <edumazet at google.com>; Nguyen, Anthony L
> <anthony.l.nguyen at intel.com>; Rob Herring <robh at kernel.org>; Leon
> Romanovsky <leon at kernel.org>; Andrew Lunn <andrew+netdev at lunn.ch>;
> linux-rdma at vger.kernel.org; Kitszel, Przemyslaw
> <przemyslaw.kitszel at intel.com>; Kubalewski, Arkadiusz
> <arkadiusz.kubalewski at intel.com>; intel-wired-lan at lists.osuosl.org;
> Jakub Kicinski <kuba at kernel.org>; Paolo Abeni <pabeni at redhat.com>;
> devicetree at vger.kernel.org; Conor Dooley <conor+dt at kernel.org>; Jiri
> Pirko <jiri at resnulli.us>; Richard Cochran <richardcochran at gmail.com>;
> Prathosh Satish <Prathosh.Satish at microchip.com>; Vadim Fedorenko
> <vadim.fedorenko at linux.dev>; Mark Bloch <mbloch at nvidia.com>; linux-
> kernel at vger.kernel.org; Tariq Toukan <tariqt at nvidia.com>; Lobakin,
> Aleksander <aleksander.lobakin at intel.com>; Jonathan Lemon
> <jonathan.lemon at gmail.com>; Krzysztof Kozlowski <krzk+dt at kernel.org>;
> Saeed Mahameed <saeedm at nvidia.com>; David S. Miller
> <davem at davemloft.net>
> Subject: [Intel-wired-lan] [PATCH net-next 12/12] ice: dpll: Support
> E825-C SyncE and dynamic pin discovery
> 
> From: Arkadiusz Kubalewski <arkadiusz.kubalewski at intel.com>
> 
> Add DPLL support for the Intel E825-C Ethernet controller. Unlike
> previous generations (E810), the E825-C connects to the platform's
> DPLL subsystem via MUX pins defined in the system firmware (Device
> Tree/ACPI).
> 
> Implement the following mechanisms to support this architecture:
> 
> 1. Dynamic Pin Discovery: Use the fwnode_dpll_pin_find() helper to
>    locate the parent MUX pins defined in the firmware.
> 
> 2. Asynchronous Registration: Since the platform DPLL driver may probe
>    independently of the network driver, utilize the DPLL notifier
> chain
>    (register_dpll_notifier). The driver listens for DPLL_PIN_CREATED
>    events to detect when the parent MUX pins become available, then
>    registers its own Recovered Clock (RCLK) pins as children of those
>    parents.
> 
> 3. Hardware Configuration: Implement the specific register access
> logic
>    for E825-C CGU (Clock Generation Unit) registers (R10, R11). This
>    includes configuring the bypass MUXes and clock dividers required
> to
>    drive SyncE signals.
> 
> 4. Split Initialization: Refactor `ice_dpll_init()` to separate the
>    static initialization path of E810 from the dynamic, firmware-
> driven
>    path required for E825-C.
> 
> Co-developed-by: Ivan Vecera <ivecera at redhat.com>
> Signed-off-by: Ivan Vecera <ivecera at redhat.com>
> Co-developed-by: Grzegorz Nitka <grzegorz.nitka at intel.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka at intel.com>
> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski at intel.com>
> ---
>  drivers/net/ethernet/intel/ice/ice_dpll.c   | 715 +++++++++++++++++--
> -
>  drivers/net/ethernet/intel/ice/ice_dpll.h   |  25 +
>  drivers/net/ethernet/intel/ice/ice_lib.c    |   3 +
>  drivers/net/ethernet/intel/ice/ice_ptp.c    |  29 +
>  drivers/net/ethernet/intel/ice/ice_ptp_hw.c |   9 +-
>  drivers/net/ethernet/intel/ice/ice_tspll.c  | 217 ++++++
> drivers/net/ethernet/intel/ice/ice_tspll.h  |  13 +-
>  drivers/net/ethernet/intel/ice/ice_type.h   |   6 +
>  8 files changed, 925 insertions(+), 92 deletions(-)
> 
> diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c
> b/drivers/net/ethernet/intel/ice/ice_dpll.c
> index 4eca62688d834..06575d42de6e9 100644
> --- a/drivers/net/ethernet/intel/ice/ice_dpll.c
> +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
> @@ -5,6 +5,7 @@

...

> +/**
> + * ice_dpll_init_fwnode_pins - initialize pins from device tree
> + * @pf: board private structure
> + * @pins: pointer to pins array
> + * @start_idx: starting index for pins
> + * @count: number of pins to initialize
> + *
> + * Initialize input pins for E825 RCLK support. The parent pins
> (rclk0,
> +rclk1)
> + * are expected to be defined in the device tree (ACPI). This
> function
> +allocates
Device Tree and ACPI are different firmware interfaces, aren't they?
Writing "device tree (ACPI)" can mislead readers about where the
fwnode-backed discovery is expected to come from.

The code looks good for me.
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov at intel.com>


> + * them in the dpll subsystem and stores their indices for later
> +registration
> + * with the rclk pin.

...

> --
> 2.52.0