[Intel-wired-lan] [PATCH iwl-net v8] igb: Fix trigger of incorrect irq in igb_xsk_wakeup

[Sanigani, SarithaX]

> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces at osuosl.org> On Behalf Of
> Vivek Behera via Intel-wired-lan
> Sent: Thursday, January 22, 2026 7:47 PM
> To: Loktionov, Aleksandr <aleksandr.loktionov at intel.com>; Keller, Jacob E
> <jacob.e.keller at intel.com>; Nguyen, Anthony L
> <anthony.l.nguyen at intel.com>; Kitszel, Przemyslaw
> <przemyslaw.kitszel at intel.com>; Fijalkowski, Maciej
> <maciej.fijalkowski at intel.com>; sriram.yagnaraman at ericsson.com;
> kurt at linutronix.de
> Cc: intel-wired-lan at lists.osuosl.org; Behera, Vivek
> <vivek.behera at siemens.com>
> Subject: [Intel-wired-lan] [PATCH iwl-net v8] igb: Fix trigger of incorrect irq in
> igb_xsk_wakeup
> 
> The current implementation in the igb_xsk_wakeup expects the Rx and Tx
> queues to share the same irq. This would lead to triggering of incorrect irq in
> split irq configuration.
> This patch addresses this issue which could impact environments with 2
> active cpu cores or when the number of queues is reduced to 2 or less
> 
> cat /proc/interrupts | grep eno2
>  167:          0          0          0          0 IR-PCI-MSIX-0000:08:00.0
>  0-edge      eno2
>  168:          0          0          0          0 IR-PCI-MSIX-0000:08:00.0
>  1-edge      eno2-rx-0
>  169:          0          0          0          0 IR-PCI-MSIX-0000:08:00.0
>  2-edge      eno2-rx-1
>  170:          0          0          0          0 IR-PCI-MSIX-0000:08:00.0
>  3-edge      eno2-tx-0
>  171:          0          0          0          0 IR-PCI-MSIX-0000:08:00.0
>  4-edge      eno2-tx-1
> 
> Furthermore it uses the flags input argument to trigger either rx, tx or both rx
> and tx irqs as specified in the ndo_xsk_wakeup api documentation
> 
> Fixes: 80f6ccf9f116 ("igb: Introduce XSK data structures and helpers")
> Signed-off-by: Vivek Behera <vivek.behera at siemens.com>
> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov at intel.com>
> Suggested-by: Maciej Fijalkowski <maciej.fijalkowski at intel.com>
> Acked-by: Maciej Fijalkowski <maciej.fijalkowski at intel.com>
> ---
> v1: https://lore.kernel.org/intel-wired-lan/20251212131454.124116-1-
> vivek.behera at siemens.com/
> v2: https://lore.kernel.org/intel-wired-lan/20251215115416.410619-1-
> vivek.behera at siemens.com/
> v3: https://lore.kernel.org/intel-wired-lan/20251220114936.140473-1-
> vivek.behera at siemens.com/
> v4: https://lore.kernel.org/intel-wired-lan/20251222115747.230521-1-
> vivek.behera at siemens.com/
> v5: https://lore.kernel.org/intel-wired-lan/20260112130349.1737901-1-
> vivek.behera at siemens.com/
> v6: https://lore.kernel.org/intel-wired-lan/20260117145112.2088217-1-
> vivek.behera at siemens.com/
> v7: https://lore.kernel.org/intel-wired-lan/20260120075053.2260190-1-
> vivek.behera at siemens.com/
> 
> changelog:
> v1
> - Initial description of the Bug and fixes made in the patch
> 
> v1 -> v2
> - Handling of RX and TX Wakeup in igc_xsk_wakeup for a split IRQ
> configuration
> - Review suggestions by Aleksander: Modified sequence to complete all
>   error checks for rx and tx before updating napi states and triggering irqs
> - Corrected trigger of TX and RX interrupts over E1000_ICS (non msix use
> case)
> - Added define for Tx interrupt trigger bit mask for E1000_ICS
> 
> v2 -> v3
> - Included applicable feedback and suggestions from igc patch
> - Fixed logic in updating eics value when  both TX and RX need wakeup
> 
> v3 -> v4
> - Added comments to explain trigerring of both TX and RX with active queue
> pairs
> - Fixed check of xsk pools in if statement
> 
> v4 -> v5
> - Introduced a simplified logic for sequential check for RX and TX
> 
> v5 -> v6
> - Further simplifications suggested by Maciej
> - Included review suggestions from reviewers
> 
> v6 -> v7
> - Removed redundant braces
> - Updated comment block to improve explanation of implemented logic
> 
> v7 -> v8
> - Added acked-by tag
> ---
>  drivers/net/ethernet/intel/igb/igb_xsk.c | 38 +++++++++++++++++++-----
>  1 file changed, 30 insertions(+), 8 deletions(-)
> 

Tested-by: Saritha Sanigani <sarithax.sanigani at intel.com> (A Contingent Worker at Intel)