[Intel-wired-lan] [PATCH v7 net-next 5/8] ice: introduce TXC DPLL device and TX ref clock pin framework for E825

[Loktionov, Aleksandr]

> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces at osuosl.org> On Behalf
> Of Grzegorz Nitka
> Sent: Thursday, April 30, 2026 11:43 AM
> To: netdev at vger.kernel.org
> Cc: Vecera, Ivan <ivecera at redhat.com>; vadim.fedorenko at linux.dev;
> kuba at kernel.org; jiri at resnulli.us; edumazet at google.com; Kitszel,
> Przemyslaw <przemyslaw.kitszel at intel.com>; richardcochran at gmail.com;
> donald.hunter at gmail.com; linux-kernel at vger.kernel.org; Kubalewski,
> Arkadiusz <arkadiusz.kubalewski at intel.com>; andrew+netdev at lunn.ch;
> intel-wired-lan at lists.osuosl.org; horms at kernel.org;
> Prathosh.Satish at microchip.com; Nguyen, Anthony L
> <anthony.l.nguyen at intel.com>; pabeni at redhat.com; davem at davemloft.net
> Subject: [Intel-wired-lan] [PATCH v7 net-next 5/8] ice: introduce TXC
> DPLL device and TX ref clock pin framework for E825
> 
> E825 devices provide a dedicated TX clock (TXC) domain which may be
> driven by multiple reference clock sources, including external board
> references and port-derived SyncE. To support future TX clock control
> and observability through the Linux DPLL subsystem, introduce a
> separate TXC DPLL device (of DPLL_TYPE_GENERIC) and a framework for
> representing TX reference clock inputs.
> 
> This change adds a new internal DPLL pin type (TXCLK) and registers TX
> reference clock pins for E825-based devices:
> - EXT_EREF0: a board-level external electrical reference
> - SYNCE: a port-derived SyncE reference described via firmware nodes
> 
> The TXC DPLL device is created and managed alongside the existing PPS
> and EEC DPLL instances. TXCLK pins are registered directly or deferred
> via a notifier when backed by fwnode-described pins.
> A per-pin attribute encodes the TX reference source associated with
> each TXCLK pin.
> 
> At this stage, TXCLK pin state callbacks and TXC DPLL lock status
> reporting are implemented as placeholders. Pin state getters always
> return DISCONNECTED, and the TXC DPLL is initialized in the UNLOCKED
> state. No hardware configuration or TX reference switching is
> performed yet.
> 
> This patch establishes the structural groundwork required for
> hardware-backed TX reference selection, verification, and
> synchronization status reporting, which will be implemented in
> subsequent patches.
> 
> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski at intel.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka at intel.com>
> ---
>  drivers/net/ethernet/intel/ice/ice_dpll.c   | 296 ++++++++++++++++++-
> -
>  drivers/net/ethernet/intel/ice/ice_dpll.h   |   6 +
>  drivers/net/ethernet/intel/ice/ice_ptp_hw.h |   7 +
>  3 files changed, 286 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c
> b/drivers/net/ethernet/intel/ice/ice_dpll.c
> index 62f75701d652..d839b50187ba 100644
> --- a/drivers/net/ethernet/intel/ice/ice_dpll.c
> +++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
> @@ -19,6 +19,11 @@
>  #define ICE_DPLL_SW_PIN_INPUT_BASE_QSFP		6
>  #define ICE_DPLL_SW_PIN_OUTPUT_BASE		0
> 
> +#define E825_EXT_EREF_PIN_IDX			0
> +#define E825_EXT_SYNCE_PIN_IDX			1
> +#define E825_RCLK_PARENT_0_PIN_IDX		0
> +#define E825_RCLK_PARENT_1_PIN_IDX		1
> +
>  #define ICE_DPLL_PIN_SW_INPUT_ABS(in_idx) \
>  	(ICE_DPLL_SW_PIN_INPUT_BASE_SFP + (in_idx))
> 
> @@ -57,6 +62,7 @@
>   * @ICE_DPLL_PIN_TYPE_OUTPUT: output pin
>   * @ICE_DPLL_PIN_TYPE_RCLK_INPUT: recovery clock input pin
>   * @ICE_DPLL_PIN_TYPE_SOFTWARE: software controlled SMA/U.FL pins


...

>  /**
> @@ -3199,19 +3276,40 @@ static bool ice_dpll_is_fwnode_pin(struct
> ice_dpll_pin *pin)
>  	return !IS_ERR_OR_NULL(pin->fwnode);
>  }
> 
> +static bool ice_dpll_fwnode_eq(const struct fwnode_handle *a,
> +			       const struct fwnode_handle *b) {
> +	return a && b && a == b;
I'm pretty sure that return a && a == b; is enough instead.


Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov at intel.com>

> +}
> +

...

>  #define E810C_QSFP_C827_0_HANDLE 2
>  #define E810C_QSFP_C827_1_HANDLE 3
> 
> --
> 2.39.3